One important characteristic of microelectronic technology is that over time integrated circuit geometry becomes smaller and smaller and circuitry density gets higher and higher, resulting in more powerful performance and more complex functionality per chip. This dramatic performance and functionality improvement, in turn, requires many more input/output (I/O) connections between a chip and a printed circuit board (PCB) that many of today's chips have hundreds, or even thousands, of interconnection pads. Even though the chip size keeps growing, the space left for each pad on the chip keeps shrinking. The shrinkage of the chip pad area has reached a degree that exceeds the capability of traditional wire bond technology to make connections from the chip to the substrate.
Flip chip (FC) technology has proved to be a more attractive approach to solving the pad area limitation problem. In a traditional FC package, a pattern of solder bumps is formed on the side of the chip that carries the integrated circuit. The same pattern of solder pads is formed on the top side of a substrate. The chip is then flipped upside down, aligning its pattern of solder bumps with the pattern of solder pads formed on the substrate, resulting in the contact of the solder bumps of the chip with the solder pads of the substrate. As the chip and the substrate are heated while in this alignment, the solder in the solder bumps and the solder pads flows together. Upon cooling, the solder forms mechanical and electrical joints (i.e., solder joints) that connect the chip to the substrate. Additionally, an underfill and a molding compound are added to the package to increase the package's structural stability.
Substrates made of different materials have different advantages. Ceramic has been chosen for FC substrates from the very beginning because of its ease of assembly and high-temperature performance. However, the high cost of ceramic substrates limits their application to high-end products such as a CPU. Due to its low cost, organic material is more commonly used in a wider spectrum of applications, such as communication and automotive products. For example, bismaleimide triazine (BT) is one of the most popular advanced laminates and is widely used in FC substrates.
The connection between the chip and the substrate is usually formed in a high temperature environment (e.g., 220° C.). The higher the CTE of a substance, the more that substance tends to contract when the substance is heated to a certain temperature and then subsequently cools down. Because of the CTE difference between the chip and the substrate, the chip and the substrate bend to different degrees, causing thermal-mechanical stress and strain. This thermal stress and strain concentrates on the solder joints between the chip and the substrate potentially causing early fatigue failure of the system if any solder joint is broken due to the thermal stress and strain concentration. This problem is more prominent with organic substrates than with ceramic substrates. For instance, while the CTE of the chip, mainly silicon, is only about 3 PPM/° C., and the CTE of ceramic material is about the same, the CTE of the BT substrate could be as high as 17 PPM/° C. in the plane of the substrate.
One approach to solve this stress and strain concentration problem is to add an underfill by completely filling the open space between the chip and the substrate with a liquid epoxy. The underfill material most commonly used in the industry has two components: an epoxy-based polymer and a filler material composed of small, hard particles. The filler material is usually a ceramic, and is usually silicon dioxide (SiO2). Upon curing, the resulting encapsulation provides thermal stress relief by spreading the concentrated stress and strain from the deformed solder joints to the underfill.
There are several ways that the underfill material is added to the open space between the chip and the substrate. A common technique is the capillary underfill (CUF) technique, wherein the underfill material is added by re-heating the FC bonded device to reduce the thermal strain and then injecting underfill material into the space between the chip and the substrate whereupon capillary action draws the underfill between the solder balls. Another technique is the “no flow” underfill (NUF) technique, wherein the underfill material is deposited onto the substrate, and the chip is subsequently pressed onto the underfill material. Yet another technique is the wafer level underfill (WUF) technique, wherein the underfill material is deposited over an entire wafer, the wafer is sawn or cut into individual chips, and the chips are attached to the substrate by raising the temperature of and melting the underfill material. Upon cooling, the underfill material attaches the chip to the substrate. Finally, another technique is the molded underfill process (MUF), wherein the underfill is injected into the space between the chip and substrate such that the underfill material surrounds and encapsulates the entire chip-substrate assembly.
Besides stress and strain concentration, another CTE-related issue is substrate warpage wherein the bottom surface of the substrate contracts more freely than the top surface of the substrate due to solder joint restraints from the chip, causing the substrate to bow into a convex shape. The degree of substrate warpage mainly depends on the size of the chip and the substrate. When the substrate size is less than 27 mm2, the substrate warpage is a less critical problem. However, for large flip chip substrates wherein the chip size could be several hundred square millimeters, the substrate warpage could easily exceed 8 mils, the standard set by the Joint Electron Device Engineering Council (JEDEC). Excessive warpage of the substrate prevents the attachment of the substrate to the PCB and is one of many factors causing low yields. Excessive warpage of the substrate may also cause chip shear and cracking because chip material generally has a low tensile strength. This problem remains substantially unsolved after underfill curing because the existing underfill material, designed primarily to deal with stress and strain concentration on the solder joints, is relatively resilient and not stiff enough to provide the substrate the needed support to prevent warpage.
In view of the foregoing discussion, it is highly desirable to provide an improved underfill material that maintains solder joint reliability while decreasing substrate warpage and chip shear and cracking.